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K3P6V2000B-SC
32M-Bit (2Mx16 /1Mx32) CMOS MASK ROM
FEATURES
* Switchable organization 2,097,152 x 16(word mode) 1,048,576 x 32(double word mode) * Fast access time Random Access : 100ns(Max.) Page Access : 30ns(Max.) * 4 double words/ 8 words page access * Supply voltage : single +3.3V * Current consumption Operating : 60mA(Max.) Standby : 30A(Max.) * Fully static operation * All inputs and outputs TTL compatible * Three state outputs * Package -. K3P6V2000B-SC : 70-SSOP-500
CMOS MASK ROM
GENERAL DESCRIPTION
The K3P6V2000B-SC is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 2,097,152x16 bit(word mode) or as 1,048,576x32 bit(double word mode) depending on WORD voltage level.(See mode selection table) This device includes page read mode function, page read mode allows 4 double words(or 8 words) of data to read fast in the same page, CE and A2 ~ A19 should not be changed. This device operates with a 3.3V power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The K3P6V2000B-SC is packaged in a 70-SSOP.
FUNCTIONAL BLOCK DIAGRAM
A19 . . . . . . . . A2 A0, A1 A-1 CE OE WORD CONTROL LOGIC X BUFFERS AND DECODER MEMORY CELL MATRIX (1,048,576x32/ 2,097,152x16)
PIN CONFIGURATION
Y BUFFERS AND DECODER
SENSE AMP. DATA OUT BUFFERS ... Q0/Q16 Q15/Q31
Pin Name A0 - A1 A2 - A19 Q0 - Q30 Q31 /A-1 WORD CE OE VCC VSS N.C
Pin Function Page Address Inputs Address Inputs Data Outputs Output 31(Double word mode)/ LSB Address(Word mode) Double word/Word mode selection Chip Enable Output Enable Power (3.3V) Ground No Connection
A0 A1 A2 A3 A4 A5 VCC Q0 Q16 Q1 Q17 VSS VCC Q2 Q18 Q3 Q19 Q4 Q20 Q5 Q21 VSS VCC Q6 Q22 Q7 Q23 VSS A6 A7 A8 A9 A10 A11 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
SSOP
70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36
N.C N.C N.C WORD OE CE VSS Q31/A-1 Q15 Q30 Q14 VSS VCC Q29 Q13 Q28 Q12 Q27 Q11 Q26 Q10 VSS VCC Q25 Q9 Q24 Q8 VCC A19 A18 A17 A16 A15 A14 A13
K3P6V2000B-SC
K3P6V2000B-SC
ABSOLUTE MAXIMUM RATINGS
Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Symbol VIN TBIAS TSTG Rating
CMOS MASK ROM
Unit V C C
-0.3 to +4.5 -10 to +85 -55 to +150
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70C)
Item Supply Voltage Supply Voltage Symbol VCC VSS Min 3.0 0 Typ 3.3 0 Max 3.6 0 Unit V V
DC CHARACTERISTICS
Parameter Operating Current Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level Output Low Voltage Level Symbol ICC ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOH=-400A IOL=2.1mA Test Conditions Min Max 60 500 30 2.0 -0.3 2.4 10 10 VCC+0.3 0.6 0.4 Unit mA A A A A V V V V
Cycle=5MHz, all outputs open
CE=OE=VIL, VIN=0.45V to 2.4V (AC Test Condition) CE=VIH, all outputs open CE=VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE H L L OE X H L WORD X X H L Q31/A-1 X X Output Input Mode Standby Operating Operating Operating Data High-Z High-Z Q0~Q31:Dout Q0~Q15 : Dout Q16~Q30 : Hi-Z Power Standby Active Active Active
CAPACITANCE(TA=25C, f=1.0MHz)
Item Output Capacitance Input Capacitance Symbol COUT CIN Test Conditions VOUT=0V VIN=0V Min Max 12 12 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
K3P6V2000B-SC
CMOS MASK ROM
AC CHARACTERISTICS(TA=0C to 70C, VCC=3.3V0.3V, unless otherwise noted.)
TEST CONDITIONS
Item Input Pulse Levels Input Rise and Fall Times Input and Output timing Levels Output Loads Value 0.45V to 2.4V 10ns 1.5V 1 TTL Gate and CL=100pF
READ CYCLE
Item Read Cycle Time Chip Enable Access Time Address Access Time Page Address Access Time Output Enable Access Time Output or Chip Disable to Output High-Z Output Hold from Address Change Symbol tRC tACE tAA tPA tOE tDF tOH 0 K3P6V2000B-SC10 Min 100 100 100 30 30 20 0 Max K3P6V2000B-SC12 Min 120 120 120 50 50 20 0 Max K3P6V2000B-SC15 Min 150 150 150 70 70 30 Max Unit ns ns ns ns ns ns ns
NOTE : Page Address is determined as below. Double word mode(WORD=VIH) ; A0, A1 Word mode(WORD=VIL) ; A -1, A0, A1
K3P6V2000B-SC
TIMING DIAGRAM
READ
ADD A0~A19 A-1(*1) tACE CE tOE OE tOH DOUT D0~D15 D16~D31(*2) VALID DATA tAA
CMOS MASK ROM
ADD1 tRC
ADD2 tDF(*3)
VALID DATA
PAGE READ
CE
tDF(*3)
OE
ADD A0,A1 A -1(*1) tAA DOUT D0~D15 D16~D31(*2)
1 st tPA VALID DATA
2 nd
3 rd
VALID DATA VALID DATA VALID DATA
NOTES : *1. Word Mode only. A-1 is Least Significant Bit Address.(WORD = VIL) *2. Double Word Mode only.(WORD = VIH) *3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.

ADD A2~A19

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